What will I learn on this module?
This module aims to further develop your capabilities in the areas of digital systems by means of high-level languages including C/C++ and Python.
The module starts by introducing digital system design and an overview of HDL tools. The concept of HLS and its application in high-level engineering design problems are then introduced, and several comparisons are carried out to highlight the difference and benefits of HLS. C/C++ programming language is presented as the HLS tool and you are given an overview of different data types, arrays, loops, and conditions in C/C++. You will learn the implementation of both sequential and combinational circuits in HLS as well as the concept of testbench and will learn how to apply the concept of testbench to real-world problems and how to simulate the real devices and digital components in your testbench. Through examples, you also will learn about FSM and design hierarchy and the benefit of clean code in a project. The HLS section then continues with the topic of parallelism, IP, and synthesis and concludes by looking at other methods of programming FPGA including SystemC, OpenCL, LabVIEW, and Matlab.
You will also cover techniques and tools that help you with developing your HLS code including:
1- Simulation
2- Debugging
3- FSM design tool
4- C/C++ standard library
This part of the module comes with a set of workshops specifically arranged to teach you how to use designated tools for simulation and programming a FPGA device using C/C++.
Another section of the module is devoted to programming FPGA using Python language also known as Pynq technology. You will start by understanding SoC and Xilinx Zynq family architectures. Then you will learn the fundamental requirements of Python for FPGA programming such as commonly used keywords and package management. The structure of Pynq is covered and implementing Python code in Jupyter is then explained through several examples and you learn how to apply your acquired knowledge to real world problems. You then will be briefly introduced to topics including digital signal processing (DSP), artificial intelligence (AL), machine learning (ML), software defined radio (SDR), and their common and cutting-edge applications in daily life and industry. The section concludes with looking at concept of embedded ARM cores in FPGA and running operating system (OS) on SoC.
How will I learn on this module?
The module will be delivered via a combination of lectures, directed and independent learning and practical workshops as well as asynchronous pre-recorded videos.
Lectures will be used to deliver the key concepts, knowledge and understanding of HLS and Pynq technologies. Regular workshops in HLS and Pynq will provide them with the vital practical experience required to support hardware design concepts and develop the skills the students will need to successfully complete the assignment.
How will I be supported academically on this module?
All taught materials will be provided on the eLearning platform, including workshop exercises, past exam questions and examples. You will also have access to pre-recorded video of all topics and workshops. You will be encouraged to ask questions and fully engage during all contact sessions, including workshops.
What will I be expected to read on this module?
All modules at Northumbria include a range of reading materials that students are expected to engage with. The reading list for this module can be found at: http://readinglists.northumbria.ac.uk
(Reading List service online guide for academic staff this containing contact details for the Reading List team – http://library.northumbria.ac.uk/readinglists)
What will I be expected to achieve?
Knowledge & Understanding:
1. Applying appropriate codes of practice and industry standards; knowledge of the use of C/C++ language, Python, programmable logic development equipment, software packages, and simulation tools. (AHEP 4 M1, M3)
Intellectual / Professional skills & abilities:
2. Design, model, simulate, and implement a range of digital hardware sub-systems using C/C++ and Pynq. (AHEP 4 M5, M6)
Personal Values Attributes (Global / Cultural awareness, Ethics, Curiosity) (PVA):
3. Doing group work to develop teamwork skills and promote collaboration; using practical workshops skills to investigate complex problems; providing the opportunity to innovate and show creativity by granting design freedom and research requirement within a solution approach (AHEP 4 M5, M16);
4. Awareness of environmental effect from high-power processing units and digital systems assessed in CW3 (M7)
How will I be assessed?
This module will be assessed as follows.
1- Coursework (CW): Project assignment 40% for LO1, LO2:
Here the students are asked to develop an HLS code to program a FPGA device to deliver a list of specifications as the project requirements.
2- Coursework (CW): Project assignment 40% for LO1, LO2:
Here the students are asked to develop a Python code to program a FPGA device to deliver a list of specifications as the project requirements.
3- Coursework (CW): Continuous group assignment 20% for LO1, LO2, LO3:
Here the students are given tasks during each workshop to consider and answer.
For assessments 1 and 2, the assignments are released in week 1 of module delivery with a deadline dictated by the university. The feedback is provided after approximately 3 weeks.
The schedule of assignment release and feedback on continuous assignments for a 12-week delivery is as follows:
Release: every workshop
Deadline: 2 weeks after each workshop
Feedback: after approximately 2 weeks
Pre-requisite(s)
None
Co-requisite(s)
None
Module abstract
In this module you will acquire knowledge of designing digital systems using high-level techniques. The module introduces high-level synthesis (HLS) to implement hardware description language (HDL) for FPGA chips. Using C/C++ programming language, you can bypass the gate-level and register-transfer level (RTL) code and build synthesizable logic blocks. Both combinational and sequential circuits will be covered and commonly used digital blocks such as multiplexer, demultiplexer, counter, shift register, memory block, stack, etc will be created using C/C++. The industry standard Xilinx Vivado/Vitis tools will be used to facilitate design, verification, and implementation of HLS code. You will also learn the benefit of using testbench, IP, and timing analysis to enhance the development procedure and efficiency. Additionally, you will be introduced to writing high-level codes to program FPGA in Python also known as Pynq technology. The concept of System on Chip (SoC) and Xilinx Zynq family are covered, and you will learn the fundamentals of Python language and Jupyter. The module also looks at finite state machine (FSM) and its HLS implementation as well as the concept of hierarchical design and clean code. Both C/C++ programming and Pynq lectures will be accompanied by designated workshop to give you the hands-on experience and knowledge of practical work.
Course info
Credits 20
Level of Study Postgraduate
Mode of Study 2 years full-time (with advanced practice in second year)
2 other options available
Department Mathematics, Physics and Electrical Engineering
Location City Campus, Northumbria University
City Newcastle
Start September 2024 or January 2025
All information is accurate at the time of sharing.
Full time Courses are primarily delivered via on-campus face to face learning but could include elements of online learning. Most courses run as planned and as promoted on our website and via our marketing materials, but if there are any substantial changes (as determined by the Competition and Markets Authority) to a course or there is the potential that course may be withdrawn, we will notify all affected applicants as soon as possible with advice and guidance regarding their options. It is also important to be aware that optional modules listed on course pages may be subject to change depending on uptake numbers each year.
Contact time is subject to increase or decrease in line with possible restrictions imposed by the government or the University in the interest of maintaining the health and safety and wellbeing of students, staff, and visitors if this is deemed necessary in future.
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